SH7144_08 Datasheet, PDF (367/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

11. Multi-Function Timer Pulse Unit (MTU)
11.7.5 Contention between TCNT Write and Increment Operations
If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence
and TCNT is not incremented.
Figure 11.72 shows the timing in this case.
Pφ
Address
Write signal
TCNT input
clock
TCNT
TCNT write cycle
T1 T2
TCNT address
N
M
TCNT write data
Figure 11.72 Contention between TCNT Write and Increment Operations
Rev.4.00 Mar. 27, 2008 Page 323 of 882
REJ09B0108-0400