SH7144_08 Datasheet, PDF (450/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

13. Serial Communication Interface (SCI)
Bit Bit Name Initial Value R/W
3
MPIE
0
R/W
2
TEIE
0
R/W
1
CKE1 0
R/W
0
CKE0 0
R/W
[Legend]
X: Don’t care
Description
Multiprocessor Interrupt Enable (enabled only when the
MP bit in SMR is 1 in asynchronous mode)
Write 0 to this bit in smart card interface mode.
When receive data including MPB = 0 is received,
receive data transfer from RSR to RDR, receive error
detection, and setting of the RDRF, FER, and ORER
flags in SSR, are not performed.
When receive data including MPB = 1 is received, the
MPB bit in SSR is set to 1, the MPIE bit is cleared to 0
automatically, and generation of RXI and ERI interrupts
(when the TIE and RIE bits in SCR are set to 1) and
FER and ORER flag setting are enabled.
Transmit End Interrupt Enable
Write 0 to this bit in smart card interface mode.
TEI cancellation can be performed by reading 1 from
the TDRE flag in SSR, then clearing it to 0 and clearing
the TEND flag to 0, or clearing the TEIE bit to 0.
Clock Enable 1 and 0
Enable or disable clock output from the SCK pin. The
clock output can be dynamically switched in GSM
mode. For details, refer to section 13.7.7, Clock Output
Control.
When the GM bit in SMR is 0:
00: Output disabled (SCK pin functions as an input pin
(ignored) or as an output pin (level is undefined))
01: Clock output
1X: Reserved
When the GM bit in SMR is 1:
00: Output fixed low
01: Clock output
10: Output fixed high
11: Clock output
Rev.4.00 Mar. 27, 2008 Page 406 of 882
REJ09B0108-0400