SH7144_08 Datasheet, PDF (452/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

13. Serial Communication Interface (SCI)
Bit Bit Name Initial Value R/W Description
6 RDRF
0
R/(W)* Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
• When serial reception ends normally and receive
data is transferred from RSR to RDR
[Clearing conditions]
• Power-on reset or software standby mode
• When 0 is written to RDRF after reading RDRF =
1
• When the DMAC is activated by a RXI interrupt
request.
• When the DTC is activated by an RXI interrupt
and transferred data from RDR while the DISEL
bit in DTMR of DTC is 0.
RDR and the RDRF flag are not affected and retain
their previous states even if the RE bit in SCR is
cleared to 0. If reception of the next data is
completed while the RDRF flag is still set to 1, an
overrun error will occur and the receive data will be
lost.
5 ORER
0
R/(W)* Overrun Error
Indicates that an overrun error occurred during
reception, causing abnormal termination.
[Setting condition]
• When the next serial reception is completed while
RDRF = 1
The receive data prior to the overrun error is retained
in RDR, and the data received subsequently is lost.
Also, subsequent serial reception cannot be
continued while the ORER flag is set to 1. In clocked
synchronous mode, serial transmission cannot be
continued either.
[Clearing conditions]
• Power-on reset or software standby mode
• When 0 is written to ORER after reading ORER =
1
The ORER flag is not affected and retains its
previous value when the RE bit in SCR is cleared to
0.
Rev.4.00 Mar. 27, 2008 Page 408 of 882
REJ09B0108-0400