SH7144_08 Datasheet, PDF (83/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

2. CPU
Instruction
Instruction Code
Operation
Execution
States T Bit
DT
Rn
0100nnnn00010000
Rn – 1 → Rn, when Rn 1
is 0, 1 → T. When Rn is
nonzero, 0 → T
Comparison
result
EXTS.B Rm,Rn
0110nnnnmmmm1110 Byte in Rm is sign-
1
—
extended → Rn
EXTS.W Rm,Rn
0110nnnnmmmm1111 Word in Rm is sign- 1
—
extended → Rn
EXTU.B Rm,Rn
0110nnnnmmmm1100 Byte in Rm is zero-
1
—
extended → Rn
EXTU.W Rm,Rn
0110nnnnmmmm1101 Word in Rm is zero- 1
—
extended → Rn
MAC.L
@Rm+,@Rn+ 0000nnnnmmmm1111
Signed operation of
(Rn) × (Rm) + MAC →
MAC 32 × 32 + 64 →
64 bits
3/(2 to 4)* —
MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 Signed operation of 3/(2)*
—
(Rn) × (Rm) + MAC →
MAC 16 × 16 + 64 →
64 bits
MUL.L Rm,Rn
0000nnnnmmmm0111 Rn × Rm → MACL,
32 × 32 → 32 bits
2 to 4* —
MULS.W Rm,Rn
0010nnnnmmmm1111 Signed operation of 1 to 3* —
Rn × Rm → MACL 16 ×
16 → 32 bits
MULU.W Rm,Rn
0010nnnnmmmm1110 Unsigned operation of 1 to 3* —
Rn × Rm → MACL 16 ×
16 → 32 bits
NEG
Rm,Rn
0110nnnnmmmm1011 0 – Rm → Rn
1
—
NEGC Rm,Rn
0110nnnnmmmm1010 0 – Rm – T → Rn,
1
Borrow → T
Borrow
SUB
Rm,Rn
0011nnnnmmmm1000 Rn – Rm → Rn
1
—
SUBC Rm,Rn
0011nnnnmmmm1010 Rn – Rm – T → Rn, 1
Borrow → T
Borrow
SUBV Rm,Rn
0011nnnnmmmm1011 Rn – Rm → Rn,
1
Underflow → T
Overflow
Note: * The normal number of execution states is shown. (The number in parentheses is the
number of states when there is contention with the preceding or following instructions.)
Rev.4.00 Mar. 27, 2008 Page 39 of 882
REJ09B0108-0400