SH7144_08 Datasheet, PDF (222/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

10. Direct Memory Access Controller (DMAC)
10.3.5 DMAC Operation Register (DMAOR)
The DMAOR is a 16-bit readable/writable register that specifies the transfer mode of the DMAC
Bit
Bit Name Initial Value R/W
15 to 10 ⎯
All 0
R
9
PR1
0
R/W
8
PR0
0
R/W
7 to 3 ⎯
All 0
2
AE
0
R
R/(W)*
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Priority Mode 1 and 0
These bits determine the priority level of channels for
execution when transfer requests are made for
several channels simultaneously.
00: CH0 > CH1 > CH2 > CH3
01: CH0 > CH2 > CH3 > CH1
10: CH2 > CH0 > CH1 > CH3
11: Round robin mode
Reserved
These bits are always read as 0. The write value
should always be 0.
Address Error Flag
Indicates that an address error has occurred during
DMA transfer. If this bit is set during a data transfer,
transfers on all channels are suspended. The CPU
cannot write a 1 to the AE bit. Clearing is effected by
0 write after 1 read.
0: No address error, DMA transfer enabled
[Clearing condition]
Write AE = 0 after reading AE = 1
1: Address error, DMA transfer disabled
[Setting condition]
Address error due to DMAC
Rev.4.00 Mar. 27, 2008 Page 178 of 882
REJ09B0108-0400