SH7144_08 Datasheet, PDF (552/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
11. Clear the IRIC flag to 0.
12. The IRIC flag is set to 1 according to the following two conditions.
A. The IRIC flag is set to 1 at the falling edge of the 8th cycle of one frame of the receive
clock.
SCL is automatically fixed low in synchronization with the internal clock until the IRIC
flag is cleared.
B. The IRIC flag is set to 1 at the rising edge of the 9th cycle of one frame of the receive
clock.
The IRTR and ICDRF flags are set to 1, indicating that one frame of data have been
completely received. The master devise continues outputting the receive clock for the next
receive data.
13. Read the IRTR flag in ICSR.
When the IRTR flag is 0, cancel wait mode by clearing the IRIC flag as described in step 14.
When the IRTR flag is 1 and the receive operation has been completed, issue the stop
condition as described in step 15.
14. When the IRTR flag is 0, clear the IRIC flag to 0 to cancel the wait operation.
To detect the completion of receive operation, go back to step 12 and read the IRIC flag.
15. Clear the WAIT bit in ICMR to 0 to cancel the wait mode, and then clear the IRIC flag to 0.
Clear the IRIC flag while WAIT is 0. (If the stop condition issuance instruction is executed by
clearing the WAIT bit to 0 after clearing the IRIC flag to 0, the stop condition may not be
output normally.)
16. Read the final receive data in ICDR.
17. Write BBSY = 0 and SCP = 0 to ICCR. When SCL is high, SDA is driven from low to high,
and the stop condition is generated.
Master transmit mode Master receive mode
SCL
(Master output)
9
SDA
A
(Slave output)
SDA
(Master output)
1
2
3
4
5
6
7
8
9
1
2
3
4
5
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
bit 7 bit 6 bit 5 bit 4 bit 3
Data 1
[3]
[3]
Data 2
A
IRIC
IRTR
[4] IRTR=0 [4] IRTR=1
ICDR
Data 1
User processing
[1] Clear TRS [2] ICDR read (dummy read)
and IRIC to 0
[5] ICDR read
(data 1)
[6] IRIC clear
(wait cancelled)
[6] IRIC clear
Figure 14.15 An Example of the Timing of Operations in Master Receive Mode
(MLS = ACKB = 0, WAIT = 1)
Rev.4.00 Mar. 27, 2008 Page 508 of 882
REJ09B0108-0400