SH7144_08 Datasheet, PDF (899/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

D. I/O Port Block Diagrams
RES
R
Q PEnDR D
C
PEDRL.WR
TIOCxx (MTU)
PEDRL.RD
TIOCxx (MTU)
Function 1
Function 2
PFC
Q PEnMD0
Q PEnMD1
Q PEnIOR
Software standby
DBGMD
SBYCR
Q Hi-Z
RES: Reset signal
PEDRL.RD: Port E data register L read signal
PEDRL.WR: Port E data register L write signal
Figure D.43 PEn/TIOCxx/Function 1/Function 2
Pins
PE0/TIOC0A/
DREQ0/TMS
PE2/TIOC0C/
DREQ1/TDI
PE4/TIOC1A/
RXD3/TCK
Symbol in Figure D.43
Available Products
SH7144
SH7145
Masked ROM
Masked ROM
version/
version/
Function Function F-ZTAT _{ROM less} F-ZTAT _{ROM less}
PEn TIOCxx 1
2
version version
version version
PE0 TIOC0A DREQ0 TMS
√
⎯
(MTU) (DMAC) (H-UDI)
PE2 TIOC0C DREQ1 TDI
√
⎯
(MTU) (DMAC) (H-UDI)
⎯
⎯
⎯
⎯
PE4 TIOC1A RXD3
TCK
√
⎯
(MTU) (SCI)
(H-UDI)
⎯
⎯
Rev.4.00 Mar. 27, 2008 Page 855 of 882
REJ09B0108-0400