SH7144_08 Datasheet, PDF (199/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

9. Bus State Controller (BSC)
9.6.2 Wait State Control
The number of wait states inserted into external space access states can be controlled using the
WCR settings. The specified number of Tw cycles are inserted as software cycles at the timing
shown in figure 9.4.
CK
Address
CSn
Read
RD
Data
Write
WRxx
Data
DACK
T1
Tw
T2
Figure 9.4 Wait State Timing of External Space Access (Software Wait Only)
Rev.4.00 Mar. 27, 2008 Page 155 of 882
REJ09B0108-0400