SH7144_08 Datasheet, PDF (751/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

23. Advanced User Debugger (AUD)
23.2 Input/Output Pins
Table 23.1 shows the AUD's input/output pins.
Table 23.1 AUD Pin Configuration
Name
AUD data
AUD reset
AUD mode
AUD clock
AUD sync signal
Abbreviation
AUDATA3 to
AUDATA0
AUDRST
AUDMD
AUDCK
AUDSYNC
Function
Branch Trace Mode
RAM Monitor Mode
Branch destination address
output
Monitor address/data
input/output
AUD reset input
AUD reset input
Mode select input (L)
Mode select input (H)
Sync clock (φ/2) output
Sync clock input
Data start position
identification signal output
Data start position
identification signal input
23.2.1 Pin Descriptions
• Pins Used in Both Modes
Pin
Description
AUDMD
The mode is selected by changing the input level at this pin.
Low: Branch trace mode
High: RAM monitor mode
The input at this pin should be changed when AUDRST is low.
AUDRST
The AUD's internal buffers and logic are initialized by inputting a low level to
this pin. When this signal goes low, the AUD enters the reset state and the
AUD's internal buffers and logic are reset. When AUDRST goes high again
after the AUDMD level settles, the AUD starts operating in the selected mode.
Rev.4.00 Mar. 27, 2008 Page 707 of 882
REJ09B0108-0400