SH7144_08 Datasheet, PDF (456/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

13. Serial Communication Interface (SCI)
Bit Bit Name Initial Value R/W Description
5
ORER 0
R/(W)* Overrun Error
Indicates that an overrun error occurred during
reception, causing abnormal termination.
[Setting condition]
• When the next serial reception is completed while
RDRF = 1
The receive data prior to the overrun error is retained
in RDR, and the data received subsequently is lost.
Also, subsequent serial reception cannot be
continued while the ORER flag is set to 1. In clocked
synchronous mode, serial transmission cannot be
continued, either.
[Clearing conditions]
• Power-on reset or software standby mode
• When 0 is written to ORER after reading ORER =
1
The ORER flag is not affected and retains its previous
state even if the RE bit in SCR is cleared to 0.
4
ERS
0
R/(W)* Error Signal Status
Indicates that the status of an error signal returned
from the receive side at transmission.
[Setting condition]
• When the low level of the error signal is sampled
[Clearing conditions]
• Power-on reset or software standby mode
• When 0 is written to ERS after reading ERS = 1
The ERS flag is not affected and retains its previous
state even if the TE bit in SCR is cleared to 0.
Rev.4.00 Mar. 27, 2008 Page 412 of 882
REJ09B0108-0400