SH7144_08 Datasheet, PDF (444/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

13. Serial Communication Interface (SCI)
Bit Bit Name Initial Value R/W Description
4
O/E
0
R/W Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
When even parity is set, parity bit addition is
performed in transmission so that the total number of
1 bits in the transmit character plus the parity bit is
even. In reception, a check is performed to see if the
total number of 1 bits in the receive character plus
parity bit is even.
1: Selects odd parity.
When odd parity is set, parity bit addition is
performed in transmission so that the total number of
1 bits in the transmit character plus the parity bit is
odd. In reception, a check is performed to see if the
total number of 1 bits in the receive character plus
the parity bit is odd.
3 STOP
0
R/W Stop Bit Length (enabled only in asynchronous
mode)
Selects the stop bit length in transmission.
0: 1 stop bit
1: 2 stop bits
In reception, only the first stop bit is checked. If the
second stop bit is 0, it is treated as the start bit of the
next transmit character.
2 MP
0
R/W Multiprocessor Mode (enabled only in asynchronous
mode)
When this bit is set to 1, the multiprocessor
communication function is enabled. The PE bit and
O/E bit settings are invalid in multiprocessor mode.
1 CKS1
0
R/W Clock Select 1 and 0
0 CKS0
0
R/W These bits select the clock source for the baud rate
generator.
00: Pφ clock (n = 0)
01: Pφ/8 clock (n = 1)
10: Pφ/32 clock (n = 2)
11: Pφ/128 clock (n = 3)
For the relation between the setting of CKS1 and
CKS2 and the baud rate, see section 13.3.9, Bit Rate
Register (BRR). n is the decimal display of the value
of n in BRR (see section 13.3.9, Bit Rate Register
(BRR)).
Rev.4.00 Mar. 27, 2008 Page 400 of 882
REJ09B0108-0400