SH7144_08 Datasheet, PDF (557/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
[7] SCL is fixed low until ICDR is read
[7] SCL is fixed low until ICDR is read ^{Stop condition generation}
SCL
(Master output)
8
9
1
2
3
4
5
6
7
8
9
SCL
(Slave output)
SDA
(Master output)
bit 0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Data (n -1)
[6]
Data (n -1)
[6]
[11]
SDA
(Slave output)
A
A
IRIC
ICDRF
ICDRS
Data (n -1)
Data (n)
ICDRR Data (n -2)
Data (n -1)
Data (n)
User processing
[8] IRIC clear [10] ICDR read (Data (n -1))
[9] Set ACKB to 1
[8] IRIC clear [10] ICDR read (Data (n))
[12] IRIC clear
Figure 14.19 An Example of the Timing of Operations in Slave Receive Mode 2
(MLS = 0, HNDS = 1)
Rev.4.00 Mar. 27, 2008 Page 513 of 882
REJ09B0108-0400