SH7144_08 Datasheet, PDF (535/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
Bit Bit Name Initial Value R/W
1 ICDRF0 0
R
0 STOPIM 0
R/W
Description
Receive Data Read Request Flag
Indicates the ICDR (ICDRR) state in receive mode.
0: Indicates that the data has already been read from
ICDR (ICDRR) or ICDR is initialized.
1: Indicates that data has been received successfully
and transferred from ICDRS to ICDRR, and the data
is not read yet.
[Setting condition]
• When data is received successfully and transferred
from ICDRS to ICDRR.
A. When data is received successfully while
ICDRF = 0 (at the rising edge of the 9th cycle of
the clock).
B. When ICDR is read in receive mode after data
was received while ICDRF = 1.
[Clearing conditions]
• When ICDR (ICDRR) is read.
• When 0 is written to the ICE bit.
Due to the condition B above, ICDRF is temporarily
cleared to 0 when ICDR (ICDRR) is read; however,
since data is transferred from ICDRS to ICDRR
immediately, ICDRF is set to 1 again.
Note that ICDR cannot be read successfully in transmit
mode (TRS = 1) because data is not transferred from
ICDRS to ICDRR. Read data from ICDR in receive
mode (TRS = 0) to read data in ICDR.
Stop Condition Detected Interrupt Mask
This bit enables/disables the issuing of stop-condition-
detected interrupt requests in the I²C bus format in the
slave mode.
0: This setting enables the IRIC flag setting and the
stop-condition-detected interrupt requests
(STOP = 1 or ESTP = 1) in the I²C bus format in
slave mode.
1: This setting disables the IRIC flag setting or the
stop-condition-detected interrupt requests in the I²C
bus format in slave mode.
Rev.4.00 Mar. 27, 2008 Page 491 of 882
REJ09B0108-0400