SH7144_08 Datasheet, PDF (921/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

Main Revisions for this Edition
Item
Page Revision (See Manual for Details)
24.3.1 Sleep Mode
727 In sleep mode, data should not be accessed by the DMAC,
Transition to Sleep Mode
DTC, or AUD.
Clearing Sleep Mode
⎯ Description deleted
• Clearing by the interrupt
(masked version and
ROM less version)
• Clearing by the
DMAC/DTC address
error (masked version
and ROM less version)
24.4.5 DMAC, DTC, or
AUD Operation in Sleep
Mode
731 Description amended
In sleep mode, data should not be accessed by the DMAC,
DTC, or AUD.
26.2 DC Characteristics 768 Table amended
Table 26.2 DC
Characteristics
Item
Schmitt trigger
input voltage
IRQ7 to IRQ0,
POE3 to POE0,
TCLKA to TCLKD,
TIOC0A to TIOC0D,
TIOC1A, TIOC1B,
TIOC2A, TIOC2B,
TIOC3A to TIOC3D,
TIOC4A to TIOC4D,
SCK3 to SCK0,
RXD3 to RXD0
Symbol
V_T+
(V_IH)
V_T–
(V_IL)
V_T+–V_T–
Min.
V_CC−0.5
—
0.2
Typ.
—
—
—
Max.
—
0.5
—
Measurement
Unit Conditions
V
V
V
26.4 A/D Converter
Characteristics
Table 26.17 A/D
Converter Characteristics
795
Table amended
Item
Non-linear error (reference value)
Offset error (reference value)
Full-scale error (reference value)
Min.
—
—
—
Typ.
—
—
—
Max.
±3.0*³*⁴*⁵/±5.0*⁶
±3.0*³*⁴*⁵/±5.0*⁶
±3.0*³*⁴*⁵/±5.0*⁶
Unit
LSB
LSB
LSB
26.5 Flash Memory
Characteristics
796, Table replaced
797
Table 26.18 Flash
Memory Characteristics
Appendix E Package
Dimensions
870 Figure replaced
Figure E.1 FP-112B
Figure E.2 FP-144F
871
Rev.4.00 Mar. 27, 2008 Page 877 of 882
REJ09B0108-0400