SH7144_08 Datasheet, PDF(43/930 Page) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

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SH7144_08 Datasheet, PDF (43/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

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Section 17 Pin Function Controller (PFC)

Table 17.1 SH7144 Multiplexed Pins (Port A) .......................................................................569

Table 17.2 SH7144 Multiplexed Pins (Port B) .......................................................................570

Table 17.3 SH7144 Multiplexed Pins (Port C) .......................................................................570

Table 17.4 SH7144 Multiplexed Pins (Port D) .......................................................................571

Table 17.5 SH7144 Multiplexed Pins (Port E) .......................................................................572

Table 17.6 SH7144 Multiplexed Pins (Port F)........................................................................572

Table 17.7 SH7145 Multiplexed Pins (Port A) .......................................................................573

Table 17.8 SH7145 Multiplexed Pins (Port B) .......................................................................574

Table 17.9 SH7145 Multiplexed Pins (Port C) .......................................................................574

Table 17.10 SH7145 Multiplexed Pins (Port D) .......................................................................575

Table 17.11 SH7145 Multiplexed Pins (Port E) .......................................................................576

Table 17.12 SH7145 Multiplexed Pins (Port F)........................................................................576

Table 17.13 SH7144 Pin Functions in Each Mode (1) .............................................................577

Table 17.13 SH7144 Pin Functions in Each Mode (2) .............................................................581

Table 17.14 SH7145 Pin Functions in Each Mode (1) .............................................................585

Table 17.14 SH7145 Pin Functions in Each Mode (2) .............................................................590

Table 17.15 Transmit Forms of Input Functions Allocated to Multiple Pins ...........................631

Section 18 I/O Ports

Table 18.1 Port A Data Register (PADR) Read/Write Operations .........................................638

Table 18.2 Port B Data Register (PBDR) Read/Write Operations..........................................641

Table 18.3 Port C Data Register (PCDR) Read/Write Operations..........................................644

Table 18.4 Port D Data Register (PDDR) Read/Write Operations .........................................649

Table 18.5 Port E Data Register L (PEDRL) Read/Write Operations ....................................653

Table 18.6 Port F Data Register (PFDR) Read/Write Operations...........................................655

Section 19 Flash Memory (F-ZTAT Version)

Table 19.1 Differences between Boot Mode and User Program Mode...................................660

Table 19.2 Pin Configuration..................................................................................................664

Table 19.3 Setting On-Board Programming Modes................................................................670

Table 19.4 Boot Mode Operation ...........................................................................................672

Table 19.5 Peripheral Clock (PÏ) Frequencies for which Automatic Adjustment of

LSI Bit Rate Is Possible ........................................................................................672

Section 22 User Debugging Interface (H-UDI)

Table 22.1 H-UDI Pins ...........................................................................................................695

Table 22.2 Serial Transfer Characteristics of H-UDI Registers..............................................696

Section 23 Advanced User Debugger (AUD)

Table 23.1 AUD Pin Configuration ........................................................................................707

Table 23.2 Ready Flag Format................................................................................................713

Rev.4.00 Mar. 27, 2008, Page xliii of xliv

REJ09B0108-0400

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