SH7144_08 Datasheet, PDF (756/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

23. Advanced User Debugger (AUD)
23.4 RAM Monitor Mode
23.4.1 Overview
In this mode, all the modules connected to this LSI's internal or external bus can be read and
written to, allowing RAM monitoring and tuning to be carried out.
When an address is written to AUDATA externally, the data corresponding to that address is
output. If an address and data are written to AUDATA, the data is transferred to the address.
23.4.2 Communication Protocol
The AUD latches the AUDATA input when AUDSYNC is asserted. The following AUDATA
input format should be used.
Input format
0000
DIR A3 to A0 ^{. . . . . .} A31 to A28 D3 to D0 ^{. . . . . .} Dn to Dn-3
Command
Address
Data (in case of write only)
B write: n = 7
W write: n = 15
L write: n = 31
Bit 3
Bit 2
Fixed at 1 0: Read
1: Write
Bit 1 Bit 0
00: Byte
01: Word
10: Longword
Spare bits (4 bits): b'0000
Figure 23.4 AUDATA Input Format
Rev.4.00 Mar. 27, 2008 Page 712 of 882
REJ09B0108-0400