SH7144_08 Datasheet, PDF (219/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

Bit Bit Name Initial Value R/W
11 RS3
0
R/W
10 RS2
0
R/W
9 RS1
0
R/W
8 RS0
0
R/W
7⎯
0
R
10. Direct Memory Access Controller (DMAC)
Description
Resource Select 3, 2, 1, 0
These bits specify the transfer request source.
0000: External request, dual address mode
0001: Prohibited
0010: External request, single address mode.
External address space → external device.
0011: External request, single address mode.
External device → external address space.
0100: Auto-request
0101: Prohibited
0110: MTU TGIA_0
0111: MTU TGIA_1
1000: MTU TGIA_2
1001: MTU TGIA_3
1010: MTU TGIA_4
1011: A/D1 ADI1
1100: SCI0 TXI_0
1101: SCI0 RXI_0
1110: SCI1 TXI_1
1111: SCI1 RXI_1
Note: External request designations are valid only
for channels 0 and 1. No transfer request
sources can be set for channels 2 or 3.
Reserved
This bit is always read as 0. The write value should
always be 0
Rev.4.00 Mar. 27, 2008 Page 175 of 882
REJ09B0108-0400