SH7144_08 Datasheet, PDF (73/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

2. CPU
2.4.3 Instruction Format
The instruction formats and the meaning of source and destination operand are described below.
The meaning of the operand depends on the instruction code. The symbols used are as follows:
• xxxx: Instruction code
• mmmm: Source register
• nnnn: Destination register
• iiii: Immediate data
• dddd: Displacement
Table 2.9 Instruction Formats
Instruction Formats
0 format
15
xxxx xxxx
0
xxxx xxxx
n format
15
xxxx nnnn
0
xxxx xxxx
m format
15
xxxx mmmm xxxx
0
xxxx
Source
Operand
—
Destination
Operand
—
Example
NOP
—
nnnn: Direct
MOVT Rn
register
Control register or nnnn: Direct
system register
register
STS MACH,Rn
Control register or nnnn: Indirect pre- STC.L SR,@-Rn
system register
decrement register
mmmm: Direct
register
Control register or LDC
system register
Rm,SR
mmmm: Indirect
post-increment
register
Control register or LDC.L @Rm+,SR
system register
mmmm: Indirect —
register
JMP @Rm
mmmm: PC relative —
using Rm
BRAF Rm
Rev.4.00 Mar. 27, 2008 Page 29 of 882
REJ09B0108-0400