SH7144_08 Datasheet, PDF (528/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
Table 14.5 The Relationship between Flags and Transfer States (Slave Mode)
MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB ICDRF ICDRE State
0 00
0
0
0
0
00 0 0
⎯
0
Idle state (flag clearing
required)
0
0 1↑
0
0
0
0↓
00 0 0
⎯
1↑
Start condition detected
0 1↑/0 1
(*¹)
0
0
0
0
⎯ 1↑ 0 0
1↑
1
SAR match in the first frame
(SARX ≠ SAR)
0 01
0
0
0
0
⎯ 1↑ 1↑ 0
1↑
1
General call address match
in the first frame (SARX ≠
H'00)
0 1↑/0 1
(*¹)
0
0
1↑ 1↑ ⎯ 0 0 0
1↑
1
SARX match in the first
frame (SAR ≠ SARX)
0 11
0
0
⎯⎯
⎯ ⎯ 0 1↑
⎯
⎯
Transmission end
(ACKE = 1 and ACKB = 1)
0 11
0
0
1↑/0 ⎯
⎯⎯ 0 0
⎯
1↑
Transmission end with
(*²)
ICDRE = 0
0 11
0
0
⎯⎯
0↓ 0↓ 0 0
⎯
0↓
ICDR write with the above
state
0 11
0
0
⎯⎯
⎯⎯ 0 0
⎯
1
Transmission end with
ICDRE = 1
0 11
0
0
⎯⎯
0↓ 0↓ 0 0
⎯
0↓
ICDR write with the above
state
0 11
0 01
0 01
0
0
1↑/0 ⎯
00 0 0
⎯
(*²)
0
0
1↑/0 ⎯
⎯⎯ ⎯ ⎯
1↑
(*²)
0
0
⎯⎯
0↓ 0↓ 0↓ ⎯
0↓
1↑
Automatic data transfer from
ICDRT to ICDRS in the
above state
⎯
Reception end with
ICDRF = 0
⎯
ICDR read with the above
state
0 01
0
0
⎯⎯
⎯⎯ ⎯ ⎯
1
⎯
Reception end with
ICDRF = 1
0 01
0
0
⎯⎯
0↓ 0↓ 0↓ ⎯
0↓
⎯
ICDR read with the above
state
0 01
0
0
1↑/0 ⎯
00 0 ⎯
1↑
⎯
Automatic data transfer from
(*²)
ICDRS to ICDRR with the
above state
0 ⎯ 0↓
1↑/0 0/1↑ ⎯ ⎯
⎯⎯ ⎯ ⎯
⎯
0↓
Stop condition detected
(*³) (*³)
Rev.4.00 Mar. 27, 2008 Page 484 of 882
REJ09B0108-0400