SH7144_08 Datasheet, PDF (191/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

9. Bus State Controller (BSC)
9.5.2 Bus Control Register 2 (BCR2)
BCR2 is a 16-bit readable/writable register that specifies the number of idle cycles and CS signal
assert extension of each CS space.
Bit Bit Name Initial Value R/W Description
15
IW31
1
14
IW30
1
R/W Idle cycles in CS3 and CS7 space cycles
R/W _{After read access to the CS3 and CS7 spaces, these bits}
insert idle cycles (1) when the write cycle to the CS3
space continues, (2) when the write cycle to the CS7
space continues, or (3) when continuous access is made
to CS spaces except for the CS3 and CS7 spaces.
00: No idle cycle inserted after access to the CS3 and
CS7 spaces
01: One idle cycle inserted after access to the CS3 and
CS7 spaces
10: Two idle cycles inserted after access to the CS3 and
CS7 spaces
11: Three idle cycles inserted after access to the CS3
and CS7 spaces
13
IW21
1
12
IW20
1
R/W Idle cycles in CS2 and CS6 space cycles
R/W _{After read access to the CS2 and CS6 spaces, these bits}
insert idle cycles (1) when the write cycle to the CS2
space continues, (2) when the write cycle to the CS6
space continues, or (3) when continuous access is made
to CS spaces except for the CS2 and CS6 spaces.
00: No idle cycle inserted after access to the CS2 and
CS6 spaces
01: One idle cycle inserted after access to the CS2 and
CS6 spaces
10: Two idle cycles inserted after access to the CS2 and
CS6 spaces
11: Three idle cycles inserted after access to the CS2
and CS6 spaces
Rev.4.00 Mar. 27, 2008 Page 147 of 882
REJ09B0108-0400