SH7144_08 Datasheet, PDF (589/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

15. A/D Converter
15.3.2 A/D Control/Status Register_0, 1 (ADCSR_0, ADCSR_1)
ADCSR for each module controls A/D conversion operations.
Bit Bit Name Initial Value R/W Description
7 ADF
0
R/(W)* A/D End Flag
A status flag that indicates the end of A/D conversion.
[Setting conditions]
• When A/D conversion ends in single mode
• When A/D conversion ends on all specified
channels in scan mode
[Clearing conditions]
• When 0 is written after reading ADF = 1
• When the DMAC or the DTC is activated by an
ADI interrupt and data is read from ADDR while
the DTMR bit in the DTC is cleared to 0
6 ADIE
0
R/W A/D Interrupt Enable
The A/D conversion end interrupt (ADI) request is
enabled when 1 is set
When changing the operating mode, first clear the
ADST bit in the A/D control registers (ADCR) to 0.
5⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
4 ADM
0
R/W A/D Operating Mode Select
Selects the A/D conversion mode.
0: Single mode
1: Scan mode
When changing the operating mode, first clear the
ADST bit in the A/D control registers (ADCR) to 0.
3⎯
1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
2⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev.4.00 Mar. 27, 2008 Page 545 of 882
REJ09B0108-0400