SH7144_08 Datasheet, PDF (530/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
14.3.6 I²C Bus Status Register (ICSR)
ICSR includes flags that indicate bus states. See also table 14.4 and table 14.5.
Bit Bit Name Initial Value R/W Description
7 ESTP 0
R/(W)* Erroneous Stop Condition Detection Flag
This bit is enabled in the I²C bus format in the slave mode.
[Setting condition]
• Detection of the stop condition during the transfer of
one frame
[Clearing conditions]
• Writing of 0 to this bit after reading ESTP = 1
• Clearing of the IRIC flag to 0
6 STOP 0
R/(W)* Normal Stop Condition Detection Flag
This bit is enabled in the I²C bus format in the slave mode.
[Setting condition]
• Detection of the stop condition after the transfer of one
frame
[Clearing conditions]
• Writing of 0 to this bit after reading STOP = 1
5 IRTR 0
• Clearing of the IRIC flag to 0
R/(W)* I²C Bus Interface Continuous Transfer Interrupt Request
Flag
The IRTR flag indicates that the I²C bus interface has
generated an interrupt for the CPU at the end of
transmission and reception one frame of data. The IRIC
flag is set to 1 at the same time as the IRTR flag is set to 1.
[Setting conditions]
• Setting of the ICDRE or ICDRF flag to 1 while AASX is
1 in the I²C bus interface in the slave mode.
• Setting of the ICDRE or ICDRF flag to 1, when in
master mode in I2C bus interface or synchronous serial
format
[Clearing conditions]
• Writing of 0 to this bit after reading IRTR = 1
• Clearing of the IRIC flag to 0 with ICE = 0
Rev.4.00 Mar. 27, 2008 Page 486 of 882
REJ09B0108-0400