SH7144_08 Datasheet, PDF (220/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

10. Direct Memory Access Controller (DMAC)
Bit Bit Name Initial Value R/W
Description
6 DS
0
(R/W)*²
DREQ Select
Sets the sampling method for the DREQ pin in
external request mode to either low-level detection or
falling-edge detection. This bit is valid only with
CHCR_0 and CHCR_1. For CHCR_2 and CHCR_3,
this bit is always read as 0 and the write value should
always be 0.
Even with channels 0 and 1, when specifying an on-
chip peripheral module or auto-request as the transfer
request source, this bit setting is ignored. The
sampling method is fixed at falling-edge detection in
cases other than auto-request.
0: Low-level detection
1: Falling-edge detection
5 TM
0
R/W
Transfer Mode
Specifies the bus mode for data transfer.
0: Cycle steal mode
1: Burst mode
4 TS1
0
3 TS0
0
R/W
Transfer Size 1, 0
R/W
Specify size of data for transfer.
00: Specifies byte size (8 bits)
01: Specifies word size (16 bits)
10: Specifies longword size (32 bits)
11: Prohibited
2 IE
0
R/W
Interrupt Enable
When this bit is set to 1, interrupt requests are
generated after the number of data transfers
specified in the DMATCR (when TE = 1).
0: Interrupt request not generated after DMATCR-
specified transfer count
1: Interrupt request enabled on completion of
DMATCR specified number of transfers
Rev.4.00 Mar. 27, 2008 Page 176 of 882
REJ09B0108-0400