SH7144_08 Datasheet, PDF (123/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

6. Interrupt Controller (INTC)
6.2 Input/Output Pins
Table 6.1 shows the INTC pin configuration.
Table 6.1 Pin Configuration
Name
Abbreviation I/O
Non-maskable interrupt input pin NMI
I
Interrupt request input pins
IRQ0 to IRQ7 I
Interrupt request output pin
IRQOUT
O
Function
Input of non-maskable interrupt
request signal
Input of maskable interrupt request
signals
Output of notification signal when an
interrupt has occurred
6.3 Register Descriptions
The interrupt controller has the following registers. For details on register addresses and register
states during each processing, refer to section 25, List of Registers.
• Interrupt control register 1 (ICR1)
• Interrupt control register 2 (ICR2)
• IRQ status register (ISR)
• Interrupt priority register A (IPRA)
• Interrupt priority register B (IPRB)
• Interrupt priority register C (IPRC)
• Interrupt priority register D (IPRD)
• Interrupt priority register E (IPRE)
• Interrupt priority register F (IPRF)
• Interrupt priority register G (IPRG)
• Interrupt priority register H (IPRH)
• Interrupt priority register I (IPRI)
• Interrupt priority register J (IPRJ)
Rev.4.00 Mar. 27, 2008 Page 79 of 882
REJ09B0108-0400