SH7144_08 Datasheet, PDF (433/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

12. Watchdog Timer
12.6 Usage Notes
12.6.1 Notes on Register Access
The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write to. The procedures for writing to and reading these registers are given
below.
Writing to TCNT and TCSR: These registers must be written by a word transfer instruction.
They cannot be written by byte transfer instructions.
TCNT and TCSR both have the same write address. The write data must be contained in the lower
byte of the written word. The upper byte must be H'5A (for TCNT) or H'A5 (for TCSR) (figure
12.6). This transfers the write data from the lower byte to TCNT or TCSR.
• Writing to TCNT
15
Address: H'FFFF8610
H'5A
87
0
Write data
• Writing to TCSR
15
Address: H'FFFF8610
H'A5
87
0
Write data
Figure 12.6 Writing to TCNT and TCSR
Writing to RSTCSR: RSTCSR must be written by a word access to address H'FFFF8612. It
cannot be written by byte transfer instructions.
Procedures for writing 0 to WOVF (bit 7) and for writing to RSTE (bit 6) and RSTS (bit 5) are
different, as shown in figure 12.7.
To write 0 to the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower
byte. This clears the WOVF bit to 0. The RSTE and RSTS bits are not affected. To write to the
RSTE and RSTS bits, the upper byte must be H'5A and the lower byte must be the write data. The
values of bits 6 and 5 of the lower byte are transferred to the RSTE and RSTS bits, respectively.
The WOVF bit is not affected.
Rev.4.00 Mar. 27, 2008 Page 389 of 882
REJ09B0108-0400