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SH7144_08 Datasheet, PDF (42/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
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Table 13.3
Table 13.4
Table 13.5
Table 13.6
Table 13.6
Table 13.6
Table 13.6
Table 13.7
Table 13.8
Table 13.9
Table 13.10
Table 13.11
Table 13.12
Table 13.13
BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ........................... 418
BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ........................... 418
BRR Settings for Various Bit Rates (Asynchronous Mode) (3) ........................... 419
BRR Settings for Various Bit Rates (Asynchronous Mode) (4) ........................... 419
Maximum Bit Rate for Each Frequency when Using Baud Rate Generator
(Asynchronous Mode) .......................................................................................... 420
Maximum Bit Rate with External Clock Input (Asynchronous Mode) ................ 421
BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (1) ............... 422
BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (2) ............... 422
BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (3) ............... 423
BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (4) ............... 423
Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) .... 424
Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode)
(When n = 0 and S = 372)..................................................................................... 425
Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)
(when S = 372)...................................................................................................... 425
Serial Transfer Formats (Asynchronous Mode).................................................... 427
SSR Status Flags and Receive Data Handling ...................................................... 434
Interrupt Sources in Serial Communication Interface Mode ................................ 461
Interrupt Sources in Smart Card Interface Mode .................................................. 462
Section 14 I2C Bus Interface (IIC) Option
Table 14.1 Pin Configuration.................................................................................................. 470
Table 14.2 Transfer Format .................................................................................................... 473
Table 14.3 Setting of the Transfer Rate .................................................................................. 476
Table 14.4 The Relationship between Flags and Transfer States (Master Mode)................... 483
Table 14.5 The Relationship between Flags and Transfer States (Slave Mode)..................... 484
Table 14.6 I2C Bus Data Format: Description of Symbols ..................................................... 494
Table 14.7 Examples of Operations in which the DTC Is Used ............................................. 525
Table 14.8 I2C Bus Timing (output of SCL and SDA) ........................................................... 528
Table 14.9 Tolerance of the SCL Rise Time (tSr) .................................................................... 529
Table 14.10 I2C Bus Timing (when the effect of tSr/tSf Is at its maximum)................................ 531
Section 15 A/D Converter
Table 15.1 Pin Configuration.................................................................................................. 543
Table 15.2 Channel Select List ............................................................................................... 546
Table 15.3 A/D Conversion Time (Single Mode)................................................................... 551
Table 15.4 A/D Conversion Time (Scan Mode) ..................................................................... 552
Table 15.5 A/D Converter Interrupt Sources .......................................................................... 553
Table 15.6 Analog Pin Specifications..................................................................................... 558
Rev.4.00 Mar. 27, 2008 Page xlii of xliv
REJ09B0108-0400