SH7144_08 Datasheet, PDF (169/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

8. Data Transfer Controller (DTC)
Activating
Source
Generator
Activating
Source
DTC Vector
Transfer
Address
DTE Bit Source
Transfer
Destination Priority
SCI0
RXI_0
H'00000438 DTED3 RDR_0
Arbitrary* High
TXI_0
H'0000043A DTED2 Arbitrary* TDR_0
SCI1
RXI_1
H'0000043C DTED1 RDR_1
Arbitrary*
TXI_1
H'0000043E DTED0 Arbitrary* TDR_1
Reserved
—
H'00000440 to —
—
—
H'00000443
A/D converter ADI1
(CH1)
H'00000444 DTEE5 ADDR1
Arbitrary*
Reserved
—
H'00000446 —
—
—
SCI2
RXI_2
H'00000448 DTEE3 RDR_2
Arbitrary*
TXI_2
H'0000044A DTEE2 Arbitrary* TDR_2
SCI3
RXI_3
H'0000044C DTEE1 RDR_3
Arbitrary*
TXI_3
H'0000044E DTEE0 Arbitrary* TDR_3
Reserved
—
H'00000450 to —
—
—
H'0000045F
IIC
ICI
H'00000460 DTEG7 ICDR
Arbitrary*
(receive) (receive)
Arbitrary* ICDR
(transmit) (transmit)
Reserved
—
H'00000462 to —
—
—
H'0000049F
Software
Write to
DTCSR
H'0400+
—
DTVEC[7:0]
Arbitrary* Arbitrary* Low
Note: * External memory, memory-mapped external devices, on-chip memory, on-chip
peripheral modules (excluding DMAC and DTC)
8.3.3 DTC Operation
Register information is stored in an on-chip RAM. When activated, the DTC reads register
information in an on-chip RAM and transfers data. After the data transfer, it writes updated
register information back to the RAM.
Pre-storage of register information in the RAM makes it possible to transfer data over any required
number of channels. The transfer mode can be specified as normal, repeat, and block transfer
mode. Setting the CHNE bit to 1 makes it possible to perform a number of transfers with a single
activation source (chain transfer).
Rev.4.00 Mar. 27, 2008 Page 125 of 882
REJ09B0108-0400