SH7144_08 Datasheet, PDF (250/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

10. Direct Memory Access Controller (DMAC)
10.5 Examples of Use
10.5.1 Example of DMA Transfer between On-Chip SCI and External Memory
In this example, on-chip serial communication interface channel 0 (SCI0) received data is
transferred to external memory using the DMAC channel 3.
Table 10.6 indicates the transfer conditions and the setting values of each of the registers.
Table 10.6 Transfer Conditions and Register Set Values for Transfer between On-chip SCI
and External Memory
Transfer Conditions
Transfer source: RDR0 of on-chip SCI0
Transfer destination: external memory
Transfer count: 64 times
Transfer source address: fixed
Transfer destination address: incremented
Transfer request source: SCI0 (RDR0)
Bus mode: cycle steal
Transfer unit: byte
Interrupt request generation at end of transfer
Channel priority ranking: 0 > 1 > 2 > 3
Register
SAR_3
DAR_3
DMATCR_3
CHCR_3
DMAOR
Value
H'FFFF81A5
H'00400000
H'00000040
H'00004D05
H'0001
Rev.4.00 Mar. 27, 2008 Page 206 of 882
REJ09B0108-0400