SH7144_08 Datasheet, PDF (197/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

9. Bus State Controller (BSC)
9.5.4 Wait Control Register 2 (WCR2)
WCR2 is a 16-bit readable/writable register that specifies the number of access cycles to the CS
space in DMA single address mode transfer.
Do not perform DMA single address transfer before setting WCR2.
Bit Bit Name Initial Value R/W
15 to 4 ⎯
All 0
R
3
DSW3 1
R/W
2
DSW2 1
R/W
1
DSW1 1
R/W
0
DSW0 1
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Number of wait cycles for access to CS space in DMA
single address mode
These bits specify the number of wait cycles (0 to 15)
for access to the CS space in DMA single address
mode. These bits are independent of the W bit in
WCR1.
0000: No wait (external wait insertion disabled)
0001: One wait (external wait insertion enabled)
:
1111: 15 waits (external waits insertion enabled)
9.5.5 RAM Emulation Register (RAMER)
RAMER is a 16-bit readable/writable register that selects the RAM area to be used when
emulating realtime programming of flash memory. For details, refer to section 19.5.5, RAM
Emulation Register (RAMER).
Rev.4.00 Mar. 27, 2008 Page 153 of 882
REJ09B0108-0400