SH7144_08 Datasheet, PDF (110/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

5. Exception Processing
4. The values fetched from the exception processing vector table are set in PC and SP, then the
program begins executing.
Be certain to always perform power-on reset processing when turning the system power on.
Power-On Reset by WDT: When a setting is made for a power-on reset to be generated in the
WDT’s watchdog timer mode, and the WDT’s TCNT overflows, the LSI becomes to be a power-
on reset state.
The POE (Port Output Enable) function registers in the MTU, the pin function controller (PFC)
registers, and I/O port registers are not initialized by the reset signal generated by the WDT (these
registers are only initialized by a power-on reset from outside of the chip).
If reset caused by the input signal at the RES pin and a reset caused by WDT overflow occur
simultaneously, the RES pin reset has priority, and the WOVF bit in RSTCSR is cleared to 0.
When WDT-initiated power-on reset processing is started, the CPU operates as follows:
1. The initial value (execution start address) of the program counter (PC) is fetched from the
exception processing vector table.
2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table.
3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3-I0) of
the status register (SR) are set to H'F (B'1111).
4. The values fetched from the exception processing vector table are set in the PC and SP, then
the program begins executing.
5.2.3 Manual Reset
When the RES pin is high and the MRES pin is driven low, the LSI becomes to be a manual reset
state. To reliably reset the LSI, the MRES pin should be kept at low for at least the duration of the
oscillation settling time that is set in WDT when in software standby mode (when the clock is
halted) or at least 25 t_cyc when the clock is operating. During manual reset, the CPU internal status
is initialized. Registers of on-chip peripheral modules are not initialized. When the LSI enters
manual reset status in the middle of a bus cycle, manual reset exception processing does not start
until the bus cycle has ended. Thus, manual resets do not abort bus cycles. However, once MRES
is driven low, hold the low level until the CPU becomes to be a manual reset mode after the bus
cycle ends. (Keep at low level for at least the longest bus cycle). See appendix A, Pin States, for
the status of individual pins during manual reset mode.
In the manual reset status, manual reset exception processing starts when the MRES pin is first
kept low for a set period of time and then returned to high. The CPU will then operate in the same
procedures as described for power-on resets.
Rev.4.00 Mar. 27, 2008 Page 66 of 882
REJ09B0108-0400