SH7144_08 Datasheet, PDF (548/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
Master transmit mode
SCL
(Master output)
9
SDA
A
(Slave output)
SDA
(Master output)
IRIC
IRTR
ICDRF
ICDRR
Master receive mode
SCL is fixed low until ICDR is read
SCL is fixed low until ICDR is read
1
2
3
4
5
6
7
8
9
12
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Data 1
[3]
A
bit 7 bit 6
Data 2
Undefined
Data 1
User processing
[1] Clear TRS to 0 [2] ICDR read (dummy read)
[1] IRIC clear
[4] IRIC clear [5] ICDR read
(data 1)
Figure 14.11 An Example of the Timing of Operations in Master Receive Mode
(MLS = WAIT = 0, HNDS = 1)
SCL
(Master output)
SDA
(Slave output)
SDA
(Master output)
7
8
bit 1 bit 0
Data 2
SCL is fixed low until ICDR is read
Stop condition generation
SCL is fixed low until stop condition is issued
9
1
2
3
4
5
6
7
8
9
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
[3]
Data 3
[8]
A
A
IRIC
IRTR
ICDRF
ICDRR
Data 1
Data 2
Data 3
User processing
[4] IRIC clear [7] ICDR read (data 2)
[6] Set ACKB to 1
[9] IRIC clear
[11] Write 0 to BBSY and SCP
(stop condition instruction
issuance)
[10] ICDR read (data 3)
Figure 14.12 An Example of the Stop Condition Issuance Timing in Master Receive Mode
(MLS = WAIT = 0, HNDS = 1)
Receive Operation with Wait:
Figure 14.13 and figure 14.14 are flowcharts that give examples of operations (WAIT = 1) in
master receive mode.
Rev.4.00 Mar. 27, 2008 Page 504 of 882
REJ09B0108-0400