SH7144_08 Datasheet, PDF (421/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

11. Multi-Function Timer Pulse Unit (MTU)
Release from High-Impedance State:
High-current pins that have entered high-impedance state due to input-level detection can be
released either by returning them to their initial state with a power-on reset, or by clearing all of
the bit 12 to 15 (POE0F to POE3F) flags of the ICSR1. High-current pins that have become high-
impedance due to output-level detection can be released either by returning them to their initial
state with a power-on reset, or by first clearing bit 9 (OCE) of the OCSR to disable output-level
compares, then clearing the bit 15 (OSF) flag. However, when returning from high-impedance
state by clearing the OSF flag, always do so only after outputting a high level from the high-
current pins (TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D). High-level outputs
can be achieved by setting the MTU internal registers.
POE Timing:
Figure 11.117 shows an example of timing from POE input to high impedance of pin.
CK
POE input
CK falling
Falling edge detected
PE9/
TIOC3B
High impedance state*
Note: * Other large-current pins (PE11/TIOC3D, PE12/TIOC4A, PE13/TIOC4B/MRES,
PE14/TIOC4C, PE15/TIOC4D/IRQOUT) also goes to the high impedance state at the same
timing
Figure 11.117 Falling Edge Detection Operation
11.9.5 Usage Notes
1. Make sure to set the input to the POE pin high, before detecting the level of the POE pin.
2. To clear the POE3F to POE0F bits in the input level control/status register 1 (ICSR1) and the
OSF bit in the output level control/status register (OCSR) to 0, read ICSR1, ICSR2, and OCSR
first. If there are bits which are read as 1, clear those bits to 0. Then write 1 to the other bits.
Rev.4.00 Mar. 27, 2008 Page 377 of 882
REJ09B0108-0400