SH7144_08 Datasheet, PDF (607/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

16. Compare Match Timer (CMT)
16.3 Operation
16.3.1 Compare Match Counter Operation
When an internal clock is selected with the CKS1, CKS0 bits of the CMCSR register and the STR
bit of CMSTR is set to 1, CMCNT begins incrementing with the selected clock. When the
CMCNT counter value matches that of the compare match constant register (CMCOR), the
CMCNT counter is cleared to H'0000 and the CMF flag of the CMCSR register is set to 1. If the
CMIE bit of the CMCSR register is set to 1 at this time, a compare match interrupt (CMI) is
requested. The CMCNT counter begins counting up again from H'0000.
Figure 16.2 shows the compare match counter operation.
CMCNT value
CMCOR
Counter cleared by CMCOR
compare match
H'0000
Time
Figure 16.2 Counter Operation
16.3.2 CMCNT Count Timing
One of four clocks (Pφ/8, Pφ/32, Pφ/128, Pφ/512) obtained by dividing the peripheral clock (Pφ)
can be selected by the CKS1 and CKS0 bits of CMCSR. Figure 16.3 shows the CMCNT count
timing.
Pφ
Internal
clock
CMCNT
input clock
CMCNT
N-1
N
N+1
Figure 16.3 Count Timing
Rev.4.00 Mar. 27, 2008 Page 563 of 882
REJ09B0108-0400