SH7144_08 Datasheet, PDF (189/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

9. Bus State Controller (BSC)
Bit Bit Name Initial Value R/W Description
6
A2LG 0
R/W CS2 and CS6 space longword
This bit specifies the CS2 and CS6 space bus size. This
bit is valid only for the SH7145.
This bit is reserved in SH7144. This bit is always read as
0 and should always be written with 0.
0: Depends on the value set with the A2SZ bit in this
register.
1: Longword (32 bits)
5
A1LG 0
R/W CS1 and CS5 space longword
This bit specifies the CS1 and CS5 space bus size. This
bit is valid only for the SH7145.
This bit is reserved in SH7144. This bit is always read as
0 and should always be written with 0.
0: Depends on the value set with the A1SZ bit in this
register.
1: Longword (32 bits)
4
A0LG 0
R/W CS0 and CS4 space longword
This bit specifies the CS0 and CS4 space bus size. This
bit is valid only for the SH7145.
This bit is reserved in SH7144. This bit is always read as
0 and should always be written with 0.
0: Depends on the value set with the A0SZ bit in this
register.
1: Longword (32 bits)
Note: A0LG is valid only in on-chip ROM enabled mode.
The CS0 and CS4 space bus size is specified
with the mode pin in on-chip ROM disabled mode.
3
A3SZ 1
R/W CS3 and CS7 space size
This bit specifies the CS3 and CS7 space bus size in
A3LG = 0.
0: Byte (8 bits)
1: Word (16 bits)
Note: In A3LG = 1, this bit is ignored and the CS3 and
CS7 space bus size is longword (32 bits).
Rev.4.00 Mar. 27, 2008 Page 145 of 882
REJ09B0108-0400