SH7144_08 Datasheet, PDF (140/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

6. Interrupt Controller (INTC)
6.7 Interrupt Response Time
Table 6.3 lists the interrupt response time, which is the time from the occurrence of an interrupt
request until the interrupt exception processing starts and fetching of the first instruction of the
interrupt service routine begins. Figure 6.5 shows an example of the pipeline operation when an
IRQ interrupt is accepted.
Table 6.3 Interrupt Response Time
Number of States
Item
NMI, Peripheral
Module
IRQ
Remarks
DMAC/DTC active
0 or 1
1
judgment
1 state required for interrupt
signals for which
DMAC/DTC activation is
possible
Interrupt priority judgment 2
3
and comparison with SR
mask bits
Wait for completion of X (≥ 0)
sequence currently being
executed by CPU
X (≥ 0)
The longest sequence is for
interrupt or address-error
exception processing (X = 4
+ m1 + m2 + m3 + m4). If
an interrupt-masking
instruction follows, however,
the time may be even
longer.
Time from start of interrupt 5 + m1 + m2 + m3
exception processing until
fetch of first instruction of
exception service routine
starts
Interrupt
response
Total: (7 or 8) + m1 +
m2 + m3+X
time
Minimum: 10
5 + m1 + m2 + m3
9 + m1 + m2 +
m3 + X
12
Performs the saving PC and
SR, and vector address
fetch.
0.20 to 0.24 µs at 50 MHz
Maximum: 12 + 2 (m1 + m2
+ m3) + m4
13 + 2 (m1 + m2
+ m3) + m4
0.38 to 0.40 µs at 50 MHz*
Note: m1 to m4 are the number of states needed for the following memory accesses.
m1: SR save (longword write)
m2: PC save (longword write)
m3: Vector address read (longword read)
m4: Fetch first instruction of interrupt service routine
* 0.38 to 0.40 µs at 50 MHz is the value in the case that m1 = m2 = m3 = m4 = 1.
Rev.4.00 Mar. 27, 2008 Page 96 of 882
REJ09B0108-0400