SH7144_08 Datasheet, PDF (221/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

10. Direct Memory Access Controller (DMAC)
Bit Bit Name Initial Value R/W
Description
1 TE
0
R/(W)*¹ Transfer End Flag
This bit is set to 1 after the number of data transfers
specified by the DMATCR. At this time, if the IE bit is
set to 1, an interrupt request is generated.
If data transfer ends before TE is set to 1 (for
example, due to an NMI or address error, or clearing
of the DE bit or DME bit of the DMAOR) the TE is not
set to 1. With this bit set to 1, data transfer is disabled
even if the DE bit is set to 1.
0: DMATCR-specified transfer count not ended
[Clearing condition]
0 write after TE = 1 read, power-on reset, software
standby mode
1: DMATCR specified number of transfers
completed
0 DE
0
R/W
DMAC Enable
DE enables operation in the corresponding channel.
0: Operation of the corresponding channel disabled
1: Operation of the corresponding channel enabled
Transfer mode is entered if this bit is set to 1 when
auto-request is specified (RS3 to RS0 settings). With
an external request or on-chip module request, when
a transfer request occurs after this bit is set to 1,
transfer is enabled. If this bit is cleared during a data
transfer, transfer is suspended.
If the DE bit has been set, but TE = 1, then if the
DME bit of the DMAOR is 0, and the NMI or AE bit of
the DMAOR is 1, transfer enable mode is not entered.
Notes: 1. TE bit: Allows only 0 write after reading 1.
2. The DI, RO, RL, AM, AL, or DS bit may be absent, depending on the channel.
Rev.4.00 Mar. 27, 2008 Page 177 of 882
REJ09B0108-0400