SH7144_08 Datasheet, PDF (12/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

7.5 Usage Notes ...................................................................................................................... 111
7.5.1 Simultaneous Fetching of Two Instructions ........................................................ 111
7.5.2 Instruction Fetches at Branches ........................................................................... 111
7.5.3 Contention between User Break and Exception Processing ................................ 112
7.5.4 Break at Non-Delay Branch Instruction Jump Destination.................................. 112
7.5.5 Module Standby Mode Setting ............................................................................ 112
Section 8 Data Transfer Controller (DTC) ........................................................113
8.1 Features............................................................................................................................. 113
8.2 Register Descriptions ........................................................................................................ 115
8.2.1 DTC Mode Register (DTMR).............................................................................. 116
8.2.2 DTC Source Address Register (DTSAR) ............................................................ 118
8.2.3 DTC Destination Address Register (DTDAR) .................................................... 118
8.2.4 DTC Initial Address Register (DTIAR)............................................................... 118
8.2.5 DTC Transfer Count Register A (DTCRA) ......................................................... 118
8.2.6 DTC Transfer Count Register B (DTCRB) ......................................................... 119
8.2.7 DTC Enable Registers (DTER)............................................................................ 119
8.2.8 DTC Control/Status Register (DTCSR)............................................................... 120
8.2.9 DTC Information Base Register (DTBR) ............................................................ 121
8.3 Operation .......................................................................................................................... 122
8.3.1 Activation Sources............................................................................................... 122
8.3.2 Location of Register Information and DTC Vector Table ................................... 122
8.3.3 DTC Operation .................................................................................................... 125
8.3.4 Interrupt Source ................................................................................................... 132
8.3.5 Operation Timing................................................................................................. 132
8.3.6 DTC Execution State Counts ............................................................................... 133
8.4 Procedures for Using DTC................................................................................................ 134
8.4.1 Activation by Interrupt......................................................................................... 134
8.4.2 Activation by Software ........................................................................................ 134
8.4.3 DTC Use Example ............................................................................................... 135
8.5 Usage Notes ...................................................................................................................... 136
8.5.1 Prohibition against DMAC/DTC Register Access by DTC................................. 136
8.5.2 Module Standby Mode Setting ............................................................................ 136
8.5.3 On-Chip RAM ..................................................................................................... 136
Section 9 Bus State Controller (BSC) ...............................................................137
9.1 Features............................................................................................................................. 137
9.2 Input/Output Pins .............................................................................................................. 139
9.3 Register Configuration...................................................................................................... 140
9.4 Address Map ..................................................................................................................... 141
Rev.4.00 Mar. 27, 2008 Page xii of xliv
REJ09B0108-0400