SH7144_08 Datasheet, PDF (543/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
11. Read the ACKB bit in ICSR.
Confirm that the slave device returns acknowledgement (ACKB bit is 0). When there is still
data to be transmitted, go to step 9 to continue the next transmission. When the slave device
does not return acknowledgement (ACKB bit is set to 1), follow step 12 to end transmission.
12. Clear the IRIC flag to 0.
Write 0 to the ACKE bit in ICCR, to clear the received ACKB bit to 0.
Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high,
and generates the stop condition.
Start condition generation
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
[5]
ICDRE
IRIC
IRTR
Interrupt
request
generation
1
2
3
4
5
6
7
8
9
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Slave address
R/W [7]
A
Interrupt
request
generation
ICDRT
Address + R/W
ICDRS
Address + R/W
1
2
bit 7 bit 6
Data 1
Data 1
Data 1
Note:
Data should not be
written to ICDR.
User processing [4] Write 1 to BBSY
and 0 to SCP
(start condition issuance)
[6] ICDR write
[6] IRIC clear
[9] ICDR write
[9] IRIC clear
Figure 14.8 An Example of the Timing of Operations in Master Transmit Mode
(MLS = WAIT = 0)
Rev.4.00 Mar. 27, 2008 Page 499 of 882
REJ09B0108-0400