SH7144_08 Datasheet, PDF (84/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

2. CPU
• Logic Operation Instructions
Instruction
Instruction Code
AND Rm,Rn
0010nnnnmmmm1001
AND #imm,R0
11001001iiiiiiii
AND.B #imm,@(R0,GBR) 11001101iiiiiiii
NOT
OR
OR
OR.B
Rm,Rn
0110nnnnmmmm0111
Rm,Rn
0010nnnnmmmm1011
#imm,R0
11001011iiiiiiii
#imm,@(R0,GBR) 11001111iiiiiiii
TAS.B @Rn
0100nnnn00011011
TST Rm,Rn
0010nnnnmmmm1000
TST #imm,R0
11001000iiiiiiii
TST.B #imm,@(R0,GBR) 11001100iiiiiiii
XOR Rm,Rn
0010nnnnmmmm1010
XOR #imm,R0
11001010iiiiiiii
XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
Operation
Execution
States T Bit
Rn & Rm → Rn
1
—
R0 & imm → R0
1
—
(R0 + GBR) & imm → 3
—
(R0 + GBR)
~Rm → Rn
1
—
Rn | Rm → Rn
1
—
R0 | imm → R0
1
—
(R0 + GBR) | imm → 3
—
(R0 + GBR)
If (Rn) is 0, 1 → T; 1 → 4
MSB of (Rn)
Test
result
Rn & Rm; if the result is 1
0, 1 → T
Test
result
R0 & imm; if the result 1
is 0, 1 → T
Test
result
(R0 + GBR) & imm; if 3
the result is 0, 1 → T
Test
result
Rn ^ Rm → Rn
1
—
R0 ^ imm → R0
1
—
(R0 + GBR) ^ imm → 3
—
(R0 + GBR)
Rev.4.00 Mar. 27, 2008 Page 40 of 882
REJ09B0108-0400