SH7144_08 Datasheet, PDF (821/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

26. Electrical Characteristics
26.3.4 Bus Timing
Table 26.6 shows bus timing.
Table 26.6 Bus Timing
Conditions: V_CC = PLLV_CC =3.3 V ± 0.3 V, AV_CC = 3.3 V ± 0.3 V, AV_CC = V_CC ± 0.3 V,
AV_ref = 3.0 V to AV_CC , V_SS = PLLV_SS = AV_SS = 0 V, T_a = –20°C to +75°C
(regular specifications), T_a = –40°C to +85°C (wide-range specifications),
When programming or erasing flash memory, T_a = –20°C to +75°C.
Item
Symbol Min.
Max. Unit Figure
Address delay time
CS delay time 1
t_AD
⎯
t_CSD1
⎯
25
ns
Figures 26.9,
28
ns
26.10
CS delay time 2
t
⎯
CSD2
28
ns
Read strobe delay time 1 t
⎯
RSD1
25
ns
Read strobe delay time 2 t
⎯
RSD2
25
ns
Read data setup time
t
15
RDS
⎯
ns
Read data hold time
t_RDH
0
⎯
ns
Write strobe delay time 1 t_WSD1
⎯
25
ns
Write strobe delay time 2 t_WSD2
⎯
25
ns
Write data delay time
t_WDD
⎯
30
ns
Write data hold time
t_WDH
0
⎯
ns
WAIT setup time
t
12
WTS
⎯
ns
Figure 26.11
WAIT hold time
t
3
WTH
⎯
ns
Read data access time
t_ACC*⁵
t
cyc
×
(n
+
2)
−
35*¹*²
⎯
ns
Figures 26.9,
Access time from read
t_OE*⁵
t
cyc
×
(n
+
1.5)
−
33*¹
⎯
ns
26.10
strobe
Address setup time (Read) t
ASR
0*³
⎯
ns
Address setup time (Write) t_ASW
0*³
⎯
ns
Address hold time (Write) t_WR
5*⁴
⎯
ns
Write data hold time
t_WRH
0*³
⎯
ns
DACK delay time
t_DACKD
⎯
28
ns
Notes: 1. The letter n means the number of waits.
2. When CS assert time is extended, this value is equal to t × (n + 3) − 35.
cyc
3. When CS assert time is extended, this value is equal to t_cyc.
4. When CS assert time is extended, this value is equal to 5 + t_cyc.
5. If access time is satisfied, there is no need that t is satisfied.
RDS
Rev.4.00 Mar. 27, 2008 Page 777 of 882
REJ09B0108-0400