SH7144_08 Datasheet, PDF (76/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

2. CPU
2.5 Instruction Set
2.5.1 Instruction Set by Classification
Table 2.10 lists the instructions according to their classification.
Table 2.10 Classification of Instructions
Operation
Classification Types Code
Function
No. of
Instructions
Data transfer 5
MOV
MOVA
Data transfer, immediate data transfer,
39
peripheral module data transfer, structure data
transfer
Effective address transfer
MOVT
T bit transfer
SWAP
Swap of upper and lower bytes
XTRCT Extraction of the middle of registers connected
Arithmetic 21
ADD
Binary addition
33
operations
ADDC
Binary addition with carry
ADDV
Binary addition with overflow check
CMP/cond Comparison
DIV1
Division
DIV0S
Initialization of signed division
DIV0U
Initialization of unsigned division
DMULS Signed double-length multiplication
DMULU Unsigned double-length multiplication
DT
Decrement and test
EXTS
Sign extension
EXTU
Zero extension
MAC
Multiply-and-accumulate, double-length
multiply-and-accumulate operation
MUL
Double-length multiply operation
MULS
Signed multiplication
MULU
Unsigned multiplication
NEG
Negation
NEGC
Negation with borrow
SUB
Binary subtraction
Rev.4.00 Mar. 27, 2008 Page 32 of 882
REJ09B0108-0400