SH7144_08 Datasheet, PDF (200/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

9. Bus State Controller (BSC)
When the wait is specified by software using WCR, the wait input WAIT signal from outside is
sampled. Figure 9.5 shows the WAIT signal sampling. The WAIT signal is sampled at the clock
rise one cycle before the clock rise when the Tw state shifts to the T2 state.
CK
Address
CSn
Read
RD
Data
Write
WRxx
Data
WAIT
DACK
T1
Tw
Tw
Two
T2
Figure 9.5 Wait State Timing of External Space Access
(Two Software Wait States + WAIT Signal Wait State)
Rev.4.00 Mar. 27, 2008 Page 156 of 882
REJ09B0108-0400