SH7144_08 Datasheet, PDF (190/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

9. Bus State Controller (BSC)
Bit Bit Name Initial Value R/W Description
2
A2SZ
1
R/W CS2 and CS6 space size
This bit specifies the CS2 and CS6 space bus size in
A2LG = 0.
0: Byte (8 bits)
1: Word (16 bits)
Note: In A2LG = 1, this bit is ignored and the CS2 and
CS6 space bus size is longword (32 bits).
1
A1SZ
1
R/W CS1 and CS5 space size
This bit specifies the CS1 and CS5 space bus size in
A1LG = 0.
0: Byte (8 bits)
1: Word (16 bits)
Note: In A1LG = 1, this bit is ignored and the CS1 and
CS5 space bus size is longword (32 bits).
0
A0SZ
1
R/W CS0 and CS4 space size
This bit specifies the CS0 and CS4 space bus size in
A0LG = 0.
0: Byte (8 bits)
1: Word (16 bits)
Note:
This bit is valid only in on-chip ROM enabled
mode. The CS0 and CS4 space bus size is
specified with the mode pin in on-chip ROM
disabled mode. Even in on-chip ROM enabled
mode, this bit is ignored in A0LG = 1, and the
CS0 and CS4 space bus size is longword (32
bits).
Rev.4.00 Mar. 27, 2008 Page 146 of 882
REJ09B0108-0400