SH7144_08 Datasheet, PDF (159/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

8. Data Transfer Controller (DTC)
8.2 Register Descriptions
The DTC has the following registers.
• DTC mode register (DTMR)
• DTC source address register (DTSAR)
• DTC destination address register (DTDAR)
• DTC initial address register (DTIAR)
• DTC transfer count register A (DTCRA)
• DTC transfer count register B (DTCRB)
These six registers cannot be directly accessed from the CPU.
When activated, the DTC transfer desired set of register information that is stored in an on-chip
RAM to the corresponding DTC registers. After the data transfer, it writes a set of updated register
information back to the RAM.
• DTC enable register A (DTEA)
• DTC enable register B (DTEB)
• DTC enable register C (DTEC)
• DTC enable register D (DTED)
• DTC enable register E (DTEE)
• DTC enable register G (DTEG)
• DTC control/status register (DTCSR)
• DTC information base register (DTBR)
For details on register addresses and register states during each processing, refer to section 25, List
of Registers.
Rev.4.00 Mar. 27, 2008 Page 115 of 882
REJ09B0108-0400