SH7144_08 Datasheet, PDF (426/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

12. Watchdog Timer
12.3.2 Timer Control/Status Register (TCSR)
TCSR is an 8-bit readable/writable register. Its functions include selecting the clock source to be
input to TCNT, and the timer mode.
Bit Bit Name Initial Value R/W Description
7 OVF
0
R/(W)*¹ Overflow Flag
Indicates that TCNT has overflowed in interval timer
mode. Only a write of 0 is permitted, to clear the
flag. This flag is not set in watchdog timer mode.
[Setting condition]
• When TCNT overflows in interval timer mode.
[Clearing condition]
6
WT/IT
0
• When writing 0 to this bit after reading this bit or
when writing 0 to the TME bit in interval timer
mode.
R/W Timer Mode Select
Selects whether the WDT is used as a watchdog
timer or interval timer. When TCNT overflows, the
WDT either generates an interval timer interrupt
(ITI) or generates a WDTOVF signal, depending on
the mode selected.
0: Interval timer mode
Interval timer interrupt (ITI) request to the CPU
when TCNT overflows
1: Watchdog timer mode
WDTOVF signal output externally when TCNT
overflows.
For details on the TCNT overflow in watchdog
timer mode, see section 12.3.3, Reset
Control/Status Register (RSTCSR).
5 TME
0
R/W Timer Enable
Enables or disables the timer.
0: Timer disabled
TCNT is initialized to H'00 and count-up stops
1: Timer enabled
TCNT starts counting. A WDTOVF signal or
interrupt is generated when TCNT overflows.
Rev.4.00 Mar. 27, 2008 Page 382 of 882
REJ09B0108-0400