SH7144_08 Datasheet, PDF (757/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

23. Advanced User Debugger (AUD)
23.4.3 Operation
Operation starts in RAM monitor mode when AUDRST is asserted, AUDMD is driven high, then
AUDRST is negated.
Figure 23.5 shows an example of a read operation, and figure 23.6 an example of a write
operation.
When AUDSYNC is asserted, input from the AUDATA pins begins. When a command, address,
or data (writing only) is input in the format shown in figure 23.4, execution of read/write access to
the specified address is started. During internal execution, the AUD returns Not Ready (0000).
When execution is completed, the Ready flag (0001) is returned (figures 23.5 and 23.6). Table
23.2 shows the Ready flag format.
In a read, data of the specified size is output when AUDSYNC is negated following detection of
this flag (figure 23.5).
If a command other than the above is input in DIR, the AUD treats this as a command error,
disables processing, and sets bit 1 in the Ready flag to 1. If a read/write operation initiated by the
command specified in DIR causes a bus error, the AUD disables processing and sets bit 2 in the
Ready flag to 1 (figure 23.7).
Bus error conditions are shown below.
1. Word access to address 4n+1 or 4n+3
2. Longword access to address 4n+1, 4n+2, or 4n+3
3. Longword access to on-chip I/O 8-bit area
4. Access to external area in single-chip mode
Table 23.2 Ready Flag Format
Bit 3
Fixed at 0
Bit 2
0: Normal status
1: Bus error
Bit 1
0: Normal status
1: Command error
Bit 0
0: Not ready
1: Ready
Rev.4.00 Mar. 27, 2008 Page 713 of 882
REJ09B0108-0400