SH7144_08 Datasheet, PDF (299/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

11. Multi-Function Timer Pulse Unit (MTU)
11.3.12 Timer Gate Control Register (TGCR)
TGCR is an 8-bit readable/writable register that controls the waveform output necessary for
brushless DC motor control in reset-synchronized PWM mode/complementary PWM mode. These
register settings are ineffective for anything other than complementary PWM mode/reset-
synchronized PWM mode.
Bit Bit Name Initial value R/W Description
7—
1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
6 BDC
0
R/W Brushless DC Motor
This bit selects whether to make the functions of this
register (TGCR) effective or ineffective.
0: Ordinary output
1: Functions of this register are made effective
5N
0
R/W Reverse Phase Output (N) Control
This bit selects whether the level output or the reset-
synchronized PWM/complementary PWM output
while the reverse pins (TIOC3D, TIOC4C, and
TIOC4D) are output.
0: Level output
1: Reset synchronized PWM/complementary PWM
output
4P
0
R/W Positive Phase Output (P) Control
This bit selects whether the level output or the reset-
synchronized PWM/complementary PWM output
while the positive pin (TIOC3B, TIOC4A, and
TIOC4B) are output.
0: Level output
1: Reset synchronized PWM/complementary PWM
output
Rev.4.00 Mar. 27, 2008 Page 255 of 882
REJ09B0108-0400