SH7144_08 Datasheet, PDF (518/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
• I²C bus format:
Addressing format with an acknowledge bit
• Synchronous serial format:
Non-addressing format without an acknowledge bit, and with master operation only
14.3.4 I²C Bus Mode Register (ICMR)
ICMR sets the transfer format and transfer rate. ICMR is only accessible when the ICE bit in
ICCR is set to 1.
Bit Bit Name Initial Value R/W Description
7 MLS
0
R/W MSB First/LSB First Select
0: MSB first
1: LSB first
When this module is used in the I²C bus format, this bit
should be set to 0.
6 WAIT
0
R/W Wait Insertion
This bit is enabled only in master mode of the I²C bus
format.
0: A wait state is not inserted, and data and the
acknowledge bit are transferred consecutively.
1: After the clock for the final bit of the data (8th cycle)
become low, the IRIC flag in ICCR is set to 1, and a
wait state is entered (with SCL at the low level).
Clearing the IRIC flag in ICCR to 0 cancels the wait
state. The acknowledge bit is then transferred.
For details, refer to section 14.4.7, Timing for Setting
IRIC and the Control of SCL.
5 CKS2
0
R/W Transfer Clock Select 2 to 0
4 CKS1
0
3 CKS0
0
R/W The CKS2 to CKS0 bits, together with the IICX0 bit in
R/W ^{SCRX, select the frequency of the transfer clock. This is}
used in the master mode. See table 14.3.
Rev.4.00 Mar. 27, 2008 Page 474 of 882
REJ09B0108-0400