SH7144_08 Datasheet, PDF (525/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
Bit Bit Name Initial Value R/W Description
1 IRIC
0
R/(W)* • I²C bus format in the slave mode
When a slave address (SVA or SVAX) matches (i.e.,
when the AAS or AASX flag is set to 1), and at the
end of data transfer up to the subsequent
retransmission start condition or stop condition
detection (i.e., at the rising edge of the 9th cycle of
transmission or receive clock)
When the general call address has been detected
(i.e., when 0 is received for R/W and the ADZ flag is
set to 1) and at the end of data reception up to the
subsequent retransmission start condition or stop
condition detection (i.e., at the rising edge of the 9th
cycle of receive clock)
When the ACKE bit is 1, and 1 is received as an
acknowledge bit
(i.e., when the ACKB bit is set to 1)
When the stop condition is detected while the
STOPIM bit is 0
(i.e., when the STOP or the ESTP flag is set to 1)
• Synchronous serial format
When the transfer of data has been completed
(i.e., at the rising edge of the 8th transmit/receive
clock)
When a start condition is detected with serial format
• When a condition occurs in which the ICDRE or
ICDRF flag is set to 1 in any operating mode.
When a start condition is detected in transmit mode
(i.e., when a start condition is detected and the
ICDRE flag is set to 1 in transmit mode)
When transmitting the data in the ICDR register buffer
(i.e., when data is transferred from ICDRT to ICDDRS
in transmit mode and the ICDRE flag is set to 1, or
data is transferred from ICDRS to ICDRR in receive
mode and the ICDRF flag is set to 1.)
[Clearing conditions]
• When 0 is written in IRIC after reading IRIC = 1
• When ICDR is read or written to by DTC
(This may not be a clearing condition. For details, see the
following operation description on DTC.)
Note: * Only 0 can be written to clear the flag.
Rev.4.00 Mar. 27, 2008 Page 481 of 882
REJ09B0108-0400