SH7144_08 Datasheet, PDF (434/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

12. Watchdog Timer
• Writing 0 to the WOVF bit
15
Address: H'FFFF8612
H'A5
87
0
H’00
• Writing to the RSTE and RSTS bits
15
Address: H'FFFF8612
H'5A
87
0
Write data
Figure 12.7 Writing to RSTCSR
Reading from TCNT, TCSR, and RSTCSR: TCNT, TCSR, and RSTCSR are read like other
registers. Use byte transfer instructions. The read addresses are H'FFFF8610 for TCSR,
H'FFFF8611 for TCNT, and H'FFFF8613 for RSTCSR.
12.6.2 TCNT Write and Increment Contention
If a timer counter increment clock pulse is generated during the T3 state of a write cycle to TCNT,
the write takes priority and the timer counter is not incremented. Figure 12.8 shows this operation.
TCNT write cycle
T1
T2
T3
φ
Address
TCNT address
Internal write
signal
TCNT input
clock
TCNT
N
M
Counter write data
Figure 12.8 Contention between TCNT Write and Increment
Rev.4.00 Mar. 27, 2008 Page 390 of 882
REJ09B0108-0400